PXD10RM Datasheet, PDF (707/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

(0x80-0xFF) is now reserved for use of the FIFO engine (see Section 18.3.3, Rx FIFO Structure).
Management of read and write pointers is done internally by the FIFO engine. The CPU can read the
received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer
structure at the beginning of the memory.
The FIFO can store up to six frames pending service by the CPU. An interrupt is sent to the CPU when
new frames are available in the FIFO. Upon receiving the interrupt, the CPU must read the frame
(accessing an MB in the 0x80 address) and then clear the interrupt. The act of clearing the interrupt triggers
the FIFO engine to replace the MB in 0x80 with the next frame in the queue, and then issue another
interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW
interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the
FIFO by reading one or more frames. A warning interrupt is also generated when four frames are
accumulated in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target application, thus
reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8
32-bit registers that can be configured to one of the following formats (see also Section 18.3.3, Rx FIFO
Structure):
• Format A: 8 extended or standard IDs (including IDE and RTR)
• Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR)
• Format C: 32 standard or extended 8-bit ID slices
NOTE
A chosen format is applied to all eight registers of the filter table. It is not
possible to mix formats within the table.
The eight elements of the filter table are individually affected by the first eight Individual Mask Registers
(RXIMR0 - RXIMR7), allowing very powerful filtering criteria to be defined. The rest of the RXIMR,
starting from RXIM8, continue to affect the regular MBs, starting from MB8. If the BCC bit is negated (or
if the RXIMR are not available for the particular MCU), then the FIFO filter table is affected by the legacy
mask registers as follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK
and the other elements (0 to 5) are affected by RXGMASK.
18.4.8 CAN Protocol Related Features
18.4.8.1 Remote Frames
Remote frame is a special kind of frame. The user can program a MB to be a Request Remote Frame by
writing the MB as Transmit with the RTR bit set to ‘1’. After the Remote Request frame is transmitted
successfully, the MB becomes a Receive Message Buffer, with the same ID as before.
When a Remote Request frame is received by FlexCAN, its ID is compared to the IDs of the transmit
message buffers with the Code field ‘1010’. If there is a matching ID, then this MB frame will be
transmitted. Note that if the matching MB has the RTR bit set, then FlexCAN will transmit a Remote
Frame as a response.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-37