PXD10RM Datasheet, PDF (426/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

layer number). The size of the graphic must be less than or equal to the size of the layer. When tile mode
is enabled, the graphic is repeated horizontally and vertically until it fills the whole layer. The horizontal
size of the tile is defined by the TILE_HOR_SIZE bit field and is restricted to be a multiple of 16 pixels.
The vertical size of the tile is defined by the TILE_VER_SIZE bit field.
The graphic data for the Tile Mode can be fetched either from the system memory or from the internal
CLUT/Tile memory. This is defined by the DATA_SEL bit field in register 4 in the control descriptor for
the layer. If the graphic is fetched from CLUT/tile memory then it must be in the CLUT/TILE RAM direct
color format. Otherwise the graphic can be in any previously described data format. See Figure 12-74 for
an example of a layer in tile mode.
Tile size - 64x64 pixels
Display Size- 320 x240 (QVGA)
Layer Size - 192 x 128 pixels
Figure 12-74. Tile Mode
When DATA_SEL is set (to use CLUT/TILE RAM) the LUOFFS bitfield defines the start address of the
tile graphic.
12.4.6 Hardware cursor
In addition to the 16 layers, the DCU also provides a special layer intended for use as a cursor. This cursor
operates in 1 bpp mode and includes its own RAM area to store the graphic. The cursor may be placed at
any location on the panel and includes an automatic blink option. The hardware cursor is configured using
a dedicated control descriptor and its visible pixels always overlay any other layer on the panel..
The size of the cursor is defined by register 1 in the control descriptor for the cursor
(CTRLDESCCURSOR_1). The register contains two bit fields, HEIGHT and WIDTH, which determine
the size and shape of the layer. Both fields are expressed in terms of the number of pixels in each
12-94
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor