PXD10RM Datasheet, PDF (1073/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

RXCTR - RX FIFO counter
POPNXTPTR - Pop Next Pointer
RX FIFO Depth - implementation specific
30.6.6 Available Status/Flag Information - SFM Mode Only
This paragraph gives an overview over the different status and flag information in the SFM Mode and their
interdependencies for different use cases. Related registers are QSPI_SFMSR and QSPI_SFMFR. Refer
to the related descriptions how to set up the QuadSPI module appropriately.
30.6.6.1 IP Bus Related Commands
Refer to Section 30.4.3.12, Instruction Code Register (QSPI_ICR)” for additional details not explicitly
covered in this paragraph.
30.6.6.1.1 IP Bus Related Commands - Normal Operation
Writing the QSPI_ICR[IC] field triggers the execution of a new command. Given that this is a legal
command the QSPI_SFMSR[IPACC] and the QSPI_SFMSR[BUSY] bits are asserted simultaneously
immediately after the execution is started.
When the instruction on the serial flash device has been finished these bits are de-asserted and the
QSPI_SFMFR[TFF] flag is set.
30.6.6.1.2 IP Bus Related Commands - Error Situations
Refer to Table 30-50 below.
30.6.6.2 AHB Bus Related Commands
Refer to Section 30.5.3.3.1, Reading Serial Flash Data into the QuadSPI Module” for additional details not
explicitly covered in this paragraph.
30.6.6.2.1 AHB Bus Related Commands - Normal Operation
Memory mapped read access to a serial flash address not covered in the AHB Buffer triggers the execution
of an AHB Command. Given that this is a legal command the QSPI_SFMSR[AHBACC] and the
QSPI_SFMSR[BUSY] bits are asserted simultaneously immediately after the execution is started.
When the instruction on the serial flash device has been finished these bits are de-asserted and the
QSPI_SFMFR[TFF] flag is set.
30.6.6.2.2 IP Bus Related Commands - Error Situations
Refer to Table 30-50 below.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-69