PXD10RM Datasheet, PDF (1179/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

For the correct movement of the SM the sine and cosine coil connections to VDDM and VDDS need to be
set properly, depending from the angular position. This is achieved by enabling and disabling of the pad
transistors T1 to T8. These pad transistors are not part of the SSD block, only the OBE (output buffer
enable) signals for the pads are provided. For the switch characteristics refer to Section 36.4.1.2.1,
Transistor Condition States”.
Aside from the pad transistors the switches S1 to S8 determine which coil provides the back EMF to the
integrator in which polarity w.r.t. the reference voltage. The switches are implemented in the analog block
of the SSD (denoted by shading them in the same manner like the analog block).
The -modulator is enabled by setting the SDCPU bit in the CONTROL register. To compensate for
switching effects of the analog circuitry the user must take into account sufficient startup time, described
in Section 36.5.1, Analog Block Startup Time” prior to starting the BIS.
36.4.1.2 Analog Wrapper + Port Control
This sub block controls the outputs to the coils and the inputs to the analog block. Refer to Figure 36-10
for details.
The most relevant bits of the CONTROL register belonging to that functional block are:
• STEP bits: These 2 bit vector has two functions.
One function is to determine which coil is driven and which coil is connected to the -modulator.
Additionally the direction of the current flow is selected with these bits. For clockwise direction of
the SM movement the value must be decremented and for counter-clockwise movement it must be
incremented when advancing from one STEP setting to the next.
• BLNDCL: This bit is the enable of the supply voltage to be routed to the coil driven in the
appropriate STEP setting during the blanking phase of an ongoing BIS.
• ITGDCL: This bit is the enable of the supply voltage to be routed to the coil driven in the
appropriate STEP setting during the integration phase of an ongoing BIS. Additionally it
determines the coil drive setting outside of any BIS.
• ITGDIR: This bit is relevant only in the integration phase. Together with the STEP bits the polarity
of the integration is determined by enabling or disabling the appropriate analog switches. Refer to
Section 36.4.1.4.3, DC Offset Cancellation”.
These control bits are translated into the appropriate switching scheme of the pad transistors and the
-modulator switches described below. Note that it must be ensured at the device level that the SSD block
has exclusive control over the analog pads connected to the SM coils.
Additionally it is a precondition that the RTZE bit in the CONTROL register is set.
36.4.1.2.1 Transistor Condition States
The pad transistors T1 to T8 are responsible for connecting the SM coils to the analog supply voltages
VDDM and VDDS. Table 36-11 below shows the pad transistor condition states implemented in the
analog block. In the table the columns have the following meaning:
• STEP denotes the setting of the corresponding bits in the CONTROL register.
• ITGST reflects the status indicator of the BIS integration phase.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-13