PXD10RM Datasheet, PDF (969/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Nexus 0x0002
Reg:
0
R _OPC
W
Reset ₀
1
2
MCK_DIV
0
0
3
4
EOC
0
0
Access: User read/write
5
6
7
8
0 PTM WEN 0
9
10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23 24 25 26 27 28 29 30 31
R
OVC
EIC
TM
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-5. Development Control Register 1 (DC1)
Table 26-5. DC1 Field Descriptions
Field
Description
0
OPC¹
Output Port Mode Control.
0 Reduced-port mode configuration (2 MDO pins).
1 Full-port mode configuration (4 MDO pins).
1–2
MCK_DIV[1:0]¹
MCKO Clock Divide Ratio (see note 1).
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
3–4
EOC[1:0]
EVTO Control.
00 EVTO upon occurrence of watchpoints (configured in DC2).
01 EVTO upon entry into debug mode.
10 EVTO upon timestamping event.
11 Reserved.
5
Reserved.
6
PTM
Program Trace Method.
0 Program trace uses traditional branch messages.
1 Program trace uses branch history messages.
7
WEN
Watchpoint Trace Enable.
0 Watchpoint messaging disabled.
1 Watchpoint messaging enabled.
8–23
Reserved.
24–26
OVC[2:0]
Overrun Control.
000 Generate overrun messages.
001–010 Reserved.
011 Delay processor for BTM / DTM / OTM overruns.
1XX Reserved.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-9