PXD10RM Datasheet, PDF (239/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

address: eMIOS1 base address +0x04
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 F23 F22 F21 F20 F19 F18 F17 F16
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. eMIOS200 Global FLAG Register (EMIOSGFLAG) for EMIOS1
F[n] — Channel [n] Flag bit
Channels that occupy a pair of slots are referred to by their lower slot number (LSB=0 standard), therefore
the bits corresponding to their higher slot number always read 0.
9.4.2.3 eMIOS200 Output Update Disable (EMIOSOUDIS)
The two modules on this device, EMIOS0 and EMIOS1, have different structures for this register as shown
in Figure 9-8 and Figure 9-9.
address: eMIOS0 base address +0x08
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 0}
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-8. eMIOS200 Output Update Disable Register (EMIOSOUDIS) for EMIOS0
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-13