PXD10RM Datasheet, PDF (746/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

20.5.2.5 Repeated START Signal
As shown in Figure 20-11, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
20.5.2.6 Arbitration Procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two
or more masters try to control the bus at the same time, a clock synchronization procedure determines the
bus clock, for which the low period is equal to the longest clock low period and the high is equal to the
shortest one among the masters. The relative priority of the contending masters is determined by a data
arbitration procedure. A bus master loses arbitration if it transmits logic “1” while another master transmits
logic “0”. The losing masters immediately switch over to slave receive mode and stop driving the SDA
output. In this case, the transition from master to slave mode does not generate a STOP condition.
Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
20.5.2.7 Clock Synchronization
Since wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and once a device's clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 20-13). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
SCL1
WAIT
Start Counting High Period
SCL2
SCL
Internal Counter Reset
Figure 20-13. I²C Bus Clock Synchronization
20-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor