PXD10RM Datasheet, PDF (1126/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 34-2. Low power configuration
Mode
Configuration
Run, Test, Safe and Stop
Standby (1)
Standby (2)
All general purpose and graphics SRAM is powered and operational.
Only 8 KB of the SRAM remains powered. Upper RAM is disabled by the MC_PCU.
All system SRAM remains powered. Upper RAM is enabled by the MC_PCU.
34.5 Register memory map
The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM.
34.6 SRAM ECC mechanism
The SRAM ECC detects the following conditions and produces the following results:
• Detects and corrects all 1-bit errors
• Detects and flags all 2-bit errors as non-correctable errors
• Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all ones, asserts an
error indicator on the bus cycle, and sets the error flag
SRAM does not detect all errors greater than 2 bits.
Internal SRAM write operations are performed on the following byte boundaries:
• 1 byte (0:7 bits)
• 2 bytes (0:15 bits)
• 4 bytes or 1 word (0:31 bits)
If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 32-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.
If the write operation is less than the entire 32-bit data width (1-, or 2-byte segment), the following occurs:
1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1-, or 2-byte segment) are merged with the corrected 32 bits on the data bus.
3. The ECC is then calculated on the resulting 32 bits formed in the previous step.
4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then
written to SRAM.
34.6.1 Access timing
The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access
during the previous clock. Table 34-3 lists the various combinations of read and write operations to SRAM
and the number of wait states used for the each operation. The table columns contain the following
information:
• Current operation: Lists the type of SRAM operation executing currently
34-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor