PXD10RM Datasheet, PDF (1151/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
15
99 0
85
99 0
PWM Output
1 Period
100 Counts
1 Period
100 Counts
MCCTL0[DITH] = 0, MCCCx[MCAM] = 0x3, MCDCx[DUTY] = 15,
MCPER[PER] = 100, MCCTL1[RECIRC] = 0
Figure 35-21. Center Aligned
35.4.1.3.2 Sign Bit (MCDCx[SIGN])
Assuming MCCTL1[RECIRC] = 0 (the active state of the PWM signal is low), when the
MCDCx[SIGN[4]] bit for the corresponding channel is cleared, MnC0P (if the PWM channel number is
even, n = 0, 1, 2...5, see Table 35-19) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2...5 see
Table 35-19), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of
the MCDCx[SIGN[4]] bit has no effect. The PWM output signal is generated on MnC0M (if the PWM
channel number is even, n = 0, 1, 2...5, see Table 35-19) or MnC1M (if the PWM channel number is odd,
n = 0, 1, 2...5).
Assuming MCCTL1[RECIRC] = 0 (the active state of the PWM signal is low), when the
MCDCx[SIGN[4]] bit for the corresponding channel is set, MnC0M (if the PWM channel number is even,
n = 0, 1, 2...5, see Table 35-19) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2...5, see
Table 35-19), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of
the MCDCx[SIGN[4]] bit has no effect. The PWM output signal is generated on MnC0P (if the PWM
channel number is even, n = 0, 1, 2...5, see Table 35-19) or MnC1P (if the PWM channel number is odd,
n = 0, 1, 2...5).
Setting MCCTL1[RECIRC] = 1 will also invert the effect of the MCDCx[SIGN[4]] bit such that while
MCDCx[SIGN[4]] = 0, MnC0P or MnC1P will generate the PWM signal and MnC0M or MnC1M will be
a static low output. While MCDCx[SIGN[4]] = 1, MnC0M or MnC1M will generate the PWM signal and
MnC0P or MnC1P will be a static low output. In this case the active state of the PWM signal will be high.
See Table 35-20 for detailed information about the impact of MCDCx[SIGN[4]] and MCCTL1[RECIRC]
bit on the PWM output.
Table 35-20. Impact of MCCTL1[RECIRC] and MCDCx[SIGN[4]] Bit on the PWM Output
Output Mode
MCCTL1[RECIRC] MCDCx[SIGN[4]]
MnCyM
MnCyP
(Dual) Full H-Bridge
0
0
PWM¹
1
(Dual) Full H-Bridge
0
1
1
PWM
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-23