PXD10RM Datasheet, PDF (254/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The Datapath block provides the channel A and B registers, the internal time base and comparators.
Multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath
in order to implement the channel modes. The outputs of A and B comparators are connected to the uc_ctrl
control block.
input input
filter
MODE
register
mode 0
logic
mode 1
logic
mode n
logic
MODE
decoder
uc_ctrl
global counter bus[A]
local counter bus
[B/C/D/E]
BSL[0]
internal counter
CNT
BSL[1]+logic
A2
BSL[1]+logic
General
Purpose
Registers
==
A Comparator
A1
uc_datapath
B2
BSL[1]+logic
B1
B Comparator
==
Figure 9-20. Unified Channel Control and Datapath Block Diagrams
9.5.1.1 UC Modes of Operation
The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the
EMIOSC[n] register (see Figure 9-19 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to disabled state
according to ODIS bit in the EMIOSC[n] register.
9-28
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor