PXD10RM Datasheet, PDF (544/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: ECSM Base + 0x60
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
REAR[0:15]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
REAR[16:31]
W
RESET: x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
= Unimplemented
Figure 16-14. RAM ECC Address (REAR) Register
Table 16-15. RAM ECC Address (REAR) Field Descriptions
Name
0-31
REAR[0:31]
Description
RAM ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled RAM ECC
event.
16.4.2.16 RAM ECC Syndrome Register (RESR)
The RESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event in
the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-15 and Table 16-16 for the RAM ECC Syndrome Register definition.
Register address: ECSM Base + 0x65
0
1
2
3
4
5
6
7
R
RESR[0:7]
W
RESET:
x
x
x
x
x
x
x
x
= Unimplemented
Figure 16-15. RAM ECC Syndrome (RESR) Register
16-18
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor