PXD10RM Datasheet, PDF (500/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: DMA_Offset + 0x1000 + (32 x n) + 0x08
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
nbytes[0:15]
W
RESET: -
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-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
nbytes[16:31]
W
RESET: -
-
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-
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-
= Unimplemented
Figure 15-21. TCDn Word 2 (TCDn.nbytes) Field (DMACR[EMLM] = 0)
Name
nbytes[0:31]
Table 15-22. TCDn Word 2 (TCDn.nbytes) field description
Description
Inner “minor” byte transfer count
Value
Number of bytes to be transferred in each service
request of the channel.
As a channel is activated, the contents of the
appropriate TCD is loaded into the DMA engine, and
the appropriate reads and writes performed until the
complete byte transfer count has been transferred. This
is an indivisible operation and cannot be stalled or
halted. After the minor count is exhausted, the current
values of the saddr and daddr are written back into the
local memory, the major iteration count is decremented
and restored to the local memory. If the major iteration
count is completed, additional processing is performed.
The nbytes value 0x0000_0000 is interpreted as
0x1_0000_0000, thus specifying a 4 GB transfer.
When minor loop mapping (DMACR[EMLM] = 1) is enabled, TCD word2 is redefined as four fields: a
source minor loop offset enable, a destination minor loop offset enable, a minor loop offset field and a
nbytes field.
15-30
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor