PXD10RM Datasheet, PDF (955/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

25.4.4 Protection of Mode Configuration Registers
While programming the mode configuration registers ME_<mode>_MC, the following rules must be
respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be
generated.
• FIRC must be on if the system clock is one of the following:
— 16MHz int. RC osc.
— div. 16MHz int. RC osc.
• FXOSC must be on if the system clock is one of the following:
— div. 4-16MHz ext. osc.
NOTE
Software must ensure to switch on the clock source that provides the input
reference clock to the FMPLL0. There is no automatic protection
mechanism to check this in the MC_ME.
• FMPLL0 must be on if the system clock is the primary freq. mod. PLL.
• Configuration “00” for the CFLAON and DFLAON bit fields are reserved.
• MVREG must be on if any of the following is active:
— FMPLL0
— CFLASH
— DFLASH
• System clock configurations marked as ‘reserved’ may not be selected.
• Configuration “1111” for the SYSCLK bit field is allowed only for the STOP and TEST modes,
and only in this case may all system clock sources be turned off.
WARNING
If the system clock is stopped during TEST mode, the device can exit only
via a system reset.
25.4.5 Mode Transition Interrupts
The following are the three interrupts related to mode transition implemented in the MC_ME.
25.4.5.1 Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules
mentioned in the Section 25.4.4, Protection of Mode Configuration Registers, the interrupt pending bit
I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of
ME_IM register is ‘1’.
25.4.5.2 Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions:
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
25-49