PXD10RM Datasheet, PDF (1295/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table B-2. Detailed register map (continued)
Register Description
Register Name
Used
Size
Address
Output Clock Division Select Register
System Clock Select Status Register
System Clock Divider Configuration Registers
System Clock Divider Configuration Registers
CGM_OCDS_SC
CGM_SC_SS
CGM_SC_DC0
CGM_SC_DC1
32-bit
32-bit
8-bit
8-bit
Base + 0x0004
Base + 0x0008
Base + 0x000C
Base + 0x000D
System Clock Divider Configuration Registers
CGM_SC_DC2
8-bit Base + 0x000E
System Clock Divider Configuration Registers
CGM_SC_DC3
8-bit Base + 0x000F
Reset Generation Module (MC_RGM) Section 32.3, Memory Map and Register Definition 0xC3FE_4000
Functional Event Status
RGM_FES
16-bit Base+0x0000
Destructive Event Status
Functional Event Reset Disable
Destructive Event Reset Disable
Reserved
Functional Event Alternate Request
Destructive Event Alternate Request
Reserved
Functional Event Short Sequence
RGM_DES
RGM_FERD
RGM_DERD
-
RGM_FEAR
RGM_DEAR
-
RGM_FESS
16-bit Base+0x0002
16-bit Base+0x0004
16-bit Base+0x0006
- (Base+0x0008) -
(Base+0x000F)
16-bit Base+0x0010
16-bit Base+0x0012
- (Base+0x0014) -
(Base+0x0017)
16-bit Base+0x0018
STANDBY reset sequence
RGM_STDBY
16-bit Base+0x001A
Functional Bidirectional Reset Enable
RGM_FBRE
16-bit Base+0x001C
Reserved
-
- (Base+0x001E) -
(Base+0x3FFF)
Power Control Unit (MC_PCU) Section 29.3, Memory Map and Register Definition
0xC3FE_8000
Power domain #0 configuration register
PCONF0
32-bit Base+0x0000
Power domain #1 configuration register
PCONF1
32-bit Base+0x0004
Power domain #1 configuration register
PCONF2
32-bit Base+0x0008
Reserved
-
- (Base+0x000C) -
(Base+0x003F)
Power Domain Status Register
PSTAT
32-bit Base+0x0040
Reserved
-
- (Base+0x0044) -
(Base+0x007C)
Voltage Regulator Control Register
Reserved
VCTL
-
32-bit Base+0x0080
- (Base+0x0084) -
(Base+0x3FFF)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
B-29