PXD10RM Datasheet, PDF (921/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
Byte and half-word write accesses are not allowed for this register as a
predefined key is required to change its value.
Table 25-5. Mode Control Register (ME_MCTL) Field Descriptions
Field
Description
TARGET_M
ODE
KEY
Target device mode — These bits provide the target device mode to be entered by software programming. The
mechanism to enter into any mode by software requires the write operation twice: first time with key, and second
time with inverted key. These bits are automatically updated by hardware while entering SAFE on hardware
request. Also, while exiting from the HALT and STOP modes on hardware exit events, these are updated with
the appropriate RUN0…3 mode value.
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT
1001 reserved
1010 STOP
1011 reserved
1100 reserved
1101 STANDBY
1110 reserved
1111 reserved
Control key — These bits enable write access to this register. Any write access to the register with a
value different from the keys is ignored. Read access will always return inverted key.
KEY: 0101101011110000 (0x5AF0)
INVERTED KEY: 1010010100001111 (0xA50F)
25.3.2.3 Mode Enable Register (ME_ME)
Address 0xC3FD_C008
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Figure 25-4. Mode Enable Register (ME_ME)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
25-15