PXD10RM Datasheet, PDF (517/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

6. Request channel service by either software (setting the TCD.start bit) or by hardware (slave device
asserting its ipd_req signal).
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine will read the entire TCD for the selected
channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the
AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source
address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until
the specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the
DMA engine's local TCD.saddr, TCD.daddr, and TCD.citer are written back to the main TCD memory and
any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post
processing is executed, i.e. interrupts, major loop channel linking, and scatter/gather operations, if enabled.
15.4.2 DMA programming errors
The DMA performs various tests on the Transfer Control Descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per channel basis with the exception of two errors; Group
Priority Error and Channel Priority Error, GPE and CPE in the DMAES register respectively.
For all error types other than Group or Channel Priority Errors, the channel number causing the error is
recorded in the DMAES register. If the error source is not removed before the next activation of the
problem channel, the error will be detected and recorded again.
The sequence listed below is correct. For item 2, the dma_ipd_ack{done} lines will assert only if the
selected channel is requesting service via the ipd_req signal. I think the typical application will enable error
interrupts for all channels. So the user will get an error interrupt, but the channel number for the DMAERR
register and the error interrupt request line may be wrong because they reflect the selected channel.
Channel priority errors are identified within a group after that group has been selected as the active group.
For example:
1. The DMA is configured for fixed group and fixed channel arbitration modes.
2. Group3 is the highest priority and all channels are unique in that group.
3. Group2 is the next highest priority and has two channels with the same priority level.
4. If Group3 has any service requests, those requests will be executed.
5. Once all of Group3 requests have completed, Group2 will be the next active group.
6. If Group2 has a service request, then an undefined channel in Group2 will be selected and a channel
priority error will occur.
7. This will repeat until the all of Group2 requests have been removed or a higher priority Group3
request comes in.
A group priority error is global and any request in any group will cause a group priority error.
In general, if priority levels are not unique, the highest (channel/group) priority that has an active request
will be selected, but the lowest numbered (channel/group) with that priority will be selected by arbitration
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-47