PXD10RM Datasheet, PDF (291/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 11-3. DSPIx_MCR Field Descriptions (continued)
Field
20
CLR_TXF
21
CLR_RXF
22–23
SMPL_
PT
[0:1]
Description
Clear TX FIFO. Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter.
The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO counter
1 Clear the TX FIFO counter
Clear RX FIFO. Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The
CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO counter
1 Clear the RX FIFO counter
Sample point. Allows the host software to select when the DSPI master samples SIN in modified
transfer format. Figure 11-16 shows where the master can sample the SIN pin. The following table
lists the delayed sample points.
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK_x and sampling of SIN_x.
00
0
01
1
10
2
11
Invalid value
24–30
31
HALT
Reserved.
Halt. Provides a mechanism for software to start and stop DSPI transfers. Refer to Section 11.8.2,
Start and Stop of DSPI Transfers, for details on the operation of this bit.
0 Start transfers
1 Stop transfers
11.7.2.2 DSPI Transfer Count Register (DSPIx_TCR)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is
running.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-9