PXD10RM Datasheet, PDF (269/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
bits IF[0:3] in EMIOSC[n] register.
EMIOSI
ipg_clk
Prescaled Clock
FCK
IF3
IF2
IF1
IF0
clk
5-bit up counter
filter out
clock
Figure 9-38. lnput Programmable Filter Submodule Diagram
The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing.
If a counter overflows occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram
of the input filter is shown in Figure 9-39.
selected clock
EMIOSI
5-bit counter
IF [0:3]= 0010
Time
filter out
Figure 9-39. Input Programmable Filter Example
The filter is not disabled during either freeze state or negated GTBE input.
9.5.1.3 Clock Prescaler (CP)
The CP divides the GCP output signal to generate a clock enable for the internal counter of the Unified
Channels. The GCP output signal is prescaled by the value defined in Figure 9-16 according to the
UCPRE[0:1] bits in EMIOSC[n] register. The prescaler is enabled by setting the UCPREN bit in the
EMIOSC[n] and can be stopped at any time by clearing this bit, thereby stopping the internal counter in
the Unified Channel.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-43