PXD10RM Datasheet, PDF (899/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 24-8. MPU_RGDn.Word3 Field Descriptions
Field
Description
0–7 Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the
PID determination of whether the current access hits in the region descriptor. This field is combined with the
PIDMASK and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
8–15
PIDMASK
Process Identifier Mask. This 8-bit field provides a masking capability so that multiple process identifiers
can be included as part of the region hit determination. If a bit in the PIDMASK is set, then the
corresponding bit of the PID is ignored in the comparison. This field is combined with the PID and
included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. For more information on the
handling of the PID and PIDMASK, see Section 24.3.1.1, Access Evaluation - Hit Determination.
31 Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit,
VLD while a write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
24.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 24.2.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2), it is expected
that since system software may adjust only the access controls within a region descriptor
(MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is
desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGDn.Word2.
Offset MPU_Base + 0x800 + (4*n) (MPU_RGDAACn)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 15 16 17 18 19 2 21 22 23 24 25 2 27 28 29 30 31
4
0
6
R_{M M M M M M M M M}
M
M
M
776655443
M3UM 2
M2UM 1
M1UM 0
M0UM
M3SM
M2SM
M1SM
M0SM
W^{R W R W R W R W P}
r wx P
r wx P
r wx P
r wx
EEEEEEEEE
E
E
E
Reset _{- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -}
Figure 24-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 24-9 are identical to those presented in Table 24-7.
Table 24-9. MPU_RGDAACn Field Descriptions
Field
Description
0
M7RE
1
M7WE
2
M6RE
Bus master 7 read enable. If set, this flag allows bus master 7 to perform read operations. If cleared, any
attempted read by bus master 7 terminates with an access error and the read is not performed.
Bus master 7 write enable. If set, this flag allows bus master 7 to perform write operations. If cleared,
any attempted write by bus master 7 terminates with an access error and the write is not performed.
Bus master 6 read enable. If set, this flag allows bus master 6 to perform read operations. If cleared, any
attempted read by bus master 6 terminates with an access error and the read is not performed.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
24-13