PXD10RM Datasheet, PDF (632/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Change the value in the UT0.MRE bit from 0 to 1.
5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0.AID bit goes high.
8. Compare UMISR0-4 content with the expected result.
9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits.
10. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0.AIS at 1 and use the linear address sequence that takes less time.
During the execution of the Margin Mode operation it is forbidden to modify the content of Block Select
(LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an
unpredictable way.
The read accesses will be done with the addition of a proper number of Wait States to guarantee the
correctness of the result.
While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check
abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 17-13. Margin Read Setup versus ‘1’s
UT0
= 0xF9F99999;
LMS
= 0x00000006;
UT0
= 0x80000004;
UT0
= 0x80000024;
UT0
= 0x80000034;
UT0
= 0x80000036;
do
{ tmp = UT0;
} while ( !(tmp & 0x00000001) );
data0 = UMISR0;
data1 = UMISR1;
data2 = UMISR2;
data3 = UMISR3;
data4 = UMISR4;
UT0
= 0x80000034;
UT0
= 0x00000000;
/* Set UTE in UT0: Enable User Test */
/* Set LSL2-1 in LMS: Select Sectors */
/* Set AIS in UT0: Select Operation */
/* Set MRE in UT0: Select Operation */
/* Set MRV in UT0: Select Margin versus 1’s */
/* Set AIE in UT0: Operation Start */
/* Loop to wait for AID=1 */
/* Read UT0 */
/* Read UMISR0 content*/
/* Read UMISR1 content*/
/* Read UMISR2 content*/
/* Read UMISR3 content*/
/* Read UMISR4 content*/
/* Reset AIE in UT0: Operation End */
/* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */
17.3.7.4.3 ECC Logic Check
ECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8 bits of ECC
syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic
of the whole page (2 Double Words).
17-82
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor