PXD10RM Datasheet, PDF (776/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

requests which have this highest priority are output as asserted interrupt requests to the associated request
selector subblock.
21.6.2.1.2 Request Selector Subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed
as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated
priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the
associated vector encoder subblock. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software configurable interrupt requests.
21.6.2.1.3 Vector Encoder Subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the
request selector subblock for the associated processor.
21.6.2.1.4 Priority Comparator Subblock
The priority comparator submodule compares the highest priority output from the priority arbitrator
submodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priority
is higher than the current priority, then it asserts the interrupt request to the processor. This interrupt request
to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the
PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new
priority which will be written to PRI in INTC_CPR when the interrupt request to the processor is
acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption
because their PRIn will not be higher than PRI in INTC_CPR.
21.6.2.2 Last-In First-Out (LIFO)
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are
stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt
exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in
softwarevector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector
mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will
not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only
14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop
‘0’s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is
regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor