PXD10RM Datasheet, PDF (225/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

8.10.5.5 Interrupt Status Register (CMU_ISR)
Address offset: 0x10
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
FHHI FLLI OLRI
r
Table 8-40. Interrupt Status Register (CMU_ISR)
rc
rc
rc
Table 8-41. Interrupt Status Register (CMU_ISR) field descriptions
Field
29
FHHI
30
FLLI
31
OLRI
Description
FMPLL0 Clock frequency higher than high reference interrupt
This bit is set by hardware when CK_FMPLL frequency becomes higher than HFREF
value and CK_FMPLL is ‘ON’ as signalled by the MC_ME. It can be cleared by software
by writing ‘1’.
0: No FHH event.
1: FHH event is pending.
FMPLL0 Clock frequency less than low reference event
This bit is set by hardware when CK_FMPLL frequency becomes lower than LFREF value
and CK_FMPLL is ‘ON’ as signalled by the MC_ME. It can be cleared by software by
writing ‘1’.
0: No FLL event.
1: FLL event is pending.
Oscillator frequency less than RC frequency event
This bit is set by hardware when the frequency of CK_FXOSC is less than
CK_FIRC/2^RCDIV frequency and CK_FXOSC is ‘ON’ as signalled by the MC_ME. It can be
cleared by software by writing ‘1’.
0: No OLR event.
1: OLR event is pending.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-47