PXD10RM Datasheet, PDF (848/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
RBSY
24
RPS
25
WUF
26
DBFF
27
DBEF
28
DRF
29
DTF
30
HRF
31
Table 23-8. LINSR field descriptions (continued)
Description
Receiver Busy Flag
0 Receiver is idle
1 Reception ongoing
Note: In Slave mode, after header reception, if DIR bit in BIDR is reset and reception starts then
this bit is set. In this case, user cannot set DTRQ bit in LINCR2.
LIN receive pin state
This bit reflects the current status of LINRX pin for diagnostic purposes.
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge
on the LINRX pin when:
• Slave is in Sleep mode
• Master is in Sleep mode or idle state
This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is
generated if WUIE bit in LINIER is set.
Data Buffer Full Flag
This bit is set by hardware and indicates the buffer is full. It is set only when receiving extended
frames (DFL > 7).
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Data Buffer Empty Flag
This bit is set by hardware and indicates the buffer is empty. It is set only when transmitting
extended frames (DFL > 7).
This bit must be cleared by software, once buffer has been filled again, in order to start
transmission.
This bit is reset by hardware in Initialization mode.
Data Reception Completed Flag
This bit is set by hardware and indicates the data reception is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error or framing error.
Data Transmission Completed Flag
This bit is set by hardware and indicates the data transmission is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error if IOBE bit is reset.
Header Reception Flag
This bit is set by hardware and indicates a valid header reception is completed.
This bit must be cleared by software.
This bit is reset by hardware in Initialization mode and at end of completed or aborted frame.
Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is
to say:
• All filters are inactive and BF bit in LINCR1 is set
• No match in any filter and BF bit in LINCR1 is set
• TX filter match
23-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor