PXD10RM Datasheet, PDF (892/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset MPU_Base + 0x000
Access: Read/Partial Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SPERR
1000
HRL
NSP
NRGD
0 0 0 0 0 0 0 VL
W
w1c
D
Reset _{0 0 0 0 0 0 0 0 1 0 0 0 * * * * * * * * * * * * 0 0 0 0 0 0 0 0}
Figure 24-2. MPU Control/Error Status Register (MPU_CESR)
Table 24-2. MPU_CESR Field Descriptions
Field
Description
0–7
SPERR
12–15
HRL
16–19
NSP
20–23
NRGD
31
VLD
Slave Port n Error, where the slave port number matches the bit number. Each bit in this field represents
a flag maintained by the MPU for signaling the presence of a captured error contained in the
MPU_EARn and MPU_EDRn registers. The individual bit is set when the hardware detects an error and
records the faulting address and attributes. It is cleared when the corresponding bit is written as a
logical one. If another error is captured at the exact same cycle as a write of a logical one, this flag
remains set. A “find first one” instruction (or equivalent) can be used to detect the presence of a
captured error.
0 The corresponding MPU_EARn/MPU_EDRn registers do not contain a captured error.
1 The corresponding MPU_EARn/MPU_EDRn registers do contain a captured error.
Hardware Revision Level. This 4-bit read-only field specifies the MPU’s hardware and definition revision
level. It can be read by software to determine the functional definition of the module.
Number of Slave Ports. This 4-bit read-only field specifies the number of slave ports [1-8] connected to
the MPU. This field contains values of 0b0001-0b1000, depending on the device configuration.
Number of Region Descriptors. This 4-bit read-only field specifies the number of region descriptors
implemented in the MPU. The defined encodings include:
0b00008 region descriptors
0b000112 region descriptors
0b001016 region descriptors
Valid. This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.
24.2.2.2 MPU Error Address Register, Slave Port n (MPU_EARn)
When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDRn register at the same time. Note this
register and the corresponding MPU_EDRn register contain the most recent access error; there are no
hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the
occurrence of each protection violation.
24-6
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor