PXD10RM Datasheet, PDF (109/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
WE0
WE1
WE2
WE3
SLB0
SLB1
SLB2
SLB3
Table 4-2. SLBRn Field Descriptions
Description
Write Enable Bits for Soft Lock Bits (SLB):
WE0 enables writing to SLB0
WE1 enables writing to SLB1
WE2 enables writing to SLB2
WE3 enables writing to SLB3
1 Value is written to SLB
0 SLB is not modified
Soft Lock Bits for one MRn register:
SLB0 can block accesses to MR[n *4 + 0]
SLB1 can block accesses to MR[n *4 + 1]
SLB2 can block accesses to MR[n *4 + 2]
SLB3 can block accesses to MR[n *4 + 3]
1 Associated MRn byte is locked against write accesses
0 Associated MRn byte is unprotected and writeable
Table 4-3 gives some examples of how SLBRn.SLB and MRn go together:
Table 4-3. Soft Lock Bits vs. Protected Address
Soft Lock Bit
SLBR0.SLB0
SLBR0.SLB1
SLBR0.SLB2
SLBR0.SLB3
SLBR1.SLB0
SLBR1.SLB1
SLBR1.SLB2
SLBR1.SLB3
SLBR2.SLB0
...
Protected address
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
MR8
...
4.1.3.2.4 Global Configuration Register (GCR)
This register is used to make global configurations related with the Register Protection.
PXD10 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-5
Preliminary—Subject to Change Without Notice