PXD10RM Datasheet, PDF (702/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Write the ID word
• Write ‘0100’ to the Code field of the Control and Status word to activate the MB
Once the MB is activated in the third step, it will be able to receive frames that match the programmed ID.
At the end of a successful reception, the MB is updated by the MBM as follows:
• The value of the Free Running Timer is written into the Time Stamp field
• The received ID, Data (8 bytes at most) and Length fields are stored
• The Code field in the Control and Status word is updated (see Table 18-5 and Table 18-6 in
Section 18.3.2, Message Buffer Structure)
• A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the
corresponding Interrupt Mask Register bit
Upon receiving the MB interrupt, the CPU should service the received frame using the following
procedure:
• Read the Control and Status word (mandatory – activates an internal lock for this buffer)
• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Read the Free Running Timer (optional – releases the internal lock)
Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU should
defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If
not executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a
single MB is locked at a time. The only mandatory CPU read operation is the one on the Control and Status
word to assure data coherency (see Section 18.4.6, Data Coherence).
The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the
interrupt flag registers (IFRL, IFRH) and not by the Code field of that MB. Polling the Code field does not
work because once a frame was received and the CPU services the MB (by reading the C/S word followed
by unlocking the MB), the Code field will not return to EMPTY. It will remain FULL, as explained in
Table 18-5. If the CPU tries to workaround this behavior by writing to the C/S word to force an EMPTY
code after reading the MB, the MB is actually deactivated from any currently ongoing matching process.
As a result, a newly received frame matching the ID of that MB may be lost. In summary: never do polling
by reading directly the C/S word of the MBs. Instead, read the interrupt flag registers (IFRL, IFRH).
Note that the received ID field is always stored in the matching MB, thus the contents of the ID field in an
MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted
by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted. If
SRX_DIS is asserted, FlexCAN will not store frames transmitted by itself in any MB, even if it contains
a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO during
Freeze Mode (see Section 18.4.7, Rx FIFO). Upon receiving the frames available interrupt from FIFO, the
CPU should service the received frame using the following procedure:
• Read the Control and Status word (optional – needed only if a mask was used for IDE and RTR
bits)
18-32
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor