PXD10RM Datasheet, PDF (191/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

These registers control the system clock dividers. The divided clock is the reference for the associated
peripheral set.
Table 8-7. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions
Field
Description
DE0
DIV0
DE1
DIV1
DE2
DIV2
Divider 0 Enable
0 Disable system clock divider 0
1 Enable system clock divider 0
Divider 0 Division Value — The resultant peripheral set 1 clock will have a period DIV0 + 1 times that of the system
clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is ignored and the peripheral
set 1 clock remains disabled.
Divider 1 Enable
0 Disable system clock divider 1
1 Enable system clock divider 1
Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of the system
clock. If the DE1 is set to ‘0’ (Divider 1 is disabled), any write access to the DIV1 field is ignored and the peripheral
set 2 clock remains disabled.
Divider 2 Enable
0 Disable system clock divider 2
1 Enable system clock divider 2
Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of the system
clock. If the DE2 is set to ‘0’ (Divider 2 is disabled), any write access to the DIV2 field is ignored and the peripheral
set 3 clock remains disabled.
8.4.3.1.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
Address 0xC3FE_0380
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
W
SELCTL
0
0
0
0
0
0
0
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
This register is used to select the current auxiliary clock 0 sources.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-13