PXD10RM Datasheet, PDF (658/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

the typical use-case where AHB p0 (the processor core) mainly accesses bank0 while the non-core AHB
masters on p1 mainly reference bank2.
In the event that both AHB ports reference the same flash bank, there is arbitration logic in the module to
determine the order the references are granted access to the targeted bank. The 2-bit PFAPR[ARBM] field
defines the port arbitration mode and this field can define a fixed priority scheme with either p0 > p1 or
p1 > p0 or a round-robin mode where the port given priority simply toggles on every simultaneous bank
conflict.
17.4.4.11 Read-While-Write Functionality
The PFLASH2P_LCA supports various programmable responses for read accesses while the flash is busy
performing a write (program) or erase operation. For all situations, the PFLASH2P_LCA uses the state of
the flash array’s bkn_fl_done output to determine if it is busy performing some type of high-voltage
operation, namely, if bkn_fl_done = 0, the array is busy.
Specifically, there are two 3-bit read-while-write (Bn_RWWC) control register fields which define the
PFLASH2P_LCA’s response to these types of access sequences. There are 5 unique responses that are
defined by the Bn_RWWC setting: one immediately reports an error on an attempted read and four settings
that support various stall-while-write capabilities. Consider the details of these settings.
• Bn_RWWC = 0b0--
— For this mode, any attempted flash read to a busy array is immediately terminated with an AHB
error response and the read is blocked in the controller and not seen by the flash array.
• Bn_RWWC = 0b111
— This defines the basic stall-while-write capability and represents the default reset setting. For
this mode, the PFLASH2P_LCA module simply stalls any read reference until the flash has
completed its program/erase operation. If a read access arrives while the array is busy or if a
falling-edge on bkn_fl_done occurs while a read is still in progress, the AHB data phase is
stalled by negating hready_out and saving the address and attributes into holding registers.
Once the array has completed its program/erase operation, the PFLASH2P_LCA uses the
saved address and attribute information to create a pseudo address phase cycle to “retry” the
read reference and sends the registered information to the array as bkn_fl_rd_en is asserted.
Once the retried address phase is complete, the read is processed normally and once the data is
valid, it is forwarded to the AHB bus and hready_out negated to terminate the system bus
transfer.
• Bn_RWWC = 0b110
— This setting is similar to the basic stall-while-write capability provided when Bn_RWWC =
0b111 with the added ability to generate a notification interrupt if a read arrives while the array
is busy with a program/erase operation. There are two notification interrupts, one for each
bank.
• Bn_RWWC = 0b101
— Again, this setting provides the basic stall-while-write capability with the added ability to abort
any program/erase operation if a read access is initiated. For this setting, the read request is
captured and retried as described for the basic stall-while-write, plus the program/erase
operation is aborted by the PFLASH2P_LCA’s assertion of the bkn_fl_abort signal. The
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor