PXD10RM Datasheet, PDF (257/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Subsequent matches are enabled with no need of further writes to EMIOSA[n] register. The FLAG is set
at the same time a match occurs.
NOTE
The channel internal counter in SAOC mode is free-running. It starts
counting as soon as the SAOC mode is entered.
EDSEL = 0
EDPOL = 1
Update to A1 A1 match
A1 match
A1 match
output flip-flop
selected counter bus
0x000500
0x001000
0x001100
0x001000
0x001100
0x001000
FLAG pin/register
A1 value¹ 0xxxxxxx 0x001000
0x001000
0x001000
0x001000
Notes: 1. EMIOSA[n] = A2
A2 = A1 according to OU[n] bit
Figure 9-23. SAOC example with EDPOL value being transferred to the output flip-flop
EDSEL = 1
EDPOL = x
Update to A1 A1 match
A1 match
output flip-flop
selected counter bus
0x000500
0x001000
0x001100
0x001000
0x001100
FLAG pin/register
A1 value¹ 0xxxxxxx 0x001000 0x001000
0x001000
Notes: 1. EMIOSA[n] = A2
A2 = A1 according to OU[n] bit
Figure 9-24. SAOC example toggling the output flip-flop
A1 match
0x001000
0x001000
EDSEL = 1
EDPOL = x
output flip-flop
selected counter bus
0x0
0x1
0x2
0x0
0x1
0x2
0x0
0x1
0x2
System Clock
A1 match
FLAG set event
FLAG pin/register
FLAG clear
A2 value¹ 0x1
Note: 1. EMIOSA[n] <= A2
9.5.1.1.4 Modulus Counter Buffered (MCB) mode
The MCB mode provides a time base which can be shared with other channels through the internal counter
buses. Register A1 is double buffered thus allowing smooth transitions between cycles when changing A2
register value on the fly. A1 register is updated at the cycle boundary, which is defined as when the internal
counter transitions to 0x1.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-31