PXD10RM Datasheet, PDF (698/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Base + 0x0030
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R _{BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF}
W ^31I
30I
29I
28I
27I
26I
25I
24I
23I
22I
21I
20I
19I
18I
17I
16I
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R _BUF
W ^15I
17
BUF
14I
18
BUF
13I
19
BUF
12I
20
BUF
11I
21 22 23 24 25 26 27 28 29 30 31
BUF BUF 9I BUF 8I BUF 7I BUF 6I BUF 5I BUF 4I BUF 3I BUF 2I BUF 1I BUF 0I
10I
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-14. Interrupt Flag Register Low (IFRL)
Table 18-17. IFRL field descriptions
Field
Description
BUF31I –
BUF8I
Buffer MB_i Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.
1 = The corresponding MB has successfully completed transmission or reception
0 = No such occurrence
BUF7I
Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag
indicates an overflow condition in the FIFO (frame lost because FIFO is full).
1 = MB7 completed transmission/reception or FIFO overflow
0 = No such occurrence
BUF6I
Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag
indicates that 4 out of 6 buffers of the FIFO are already occupied (FIFO almost full).
1 = MB6 completed transmission/reception or FIFO almost full
0 = No such occurrence
BUF5I
Buffer MB5 Interrupt or “Frames available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag
indicates that at least one frame is available to be read from the FIFO.
1 = MB5 completed transmission/reception or frames available in the FIFO
0 = No such occurrence
BUF4I – BUF0I Buffer MB_i Interrupt or “reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these
flags are not used and must be considered as reserved locations.
1 = Corresponding MB completed transmission/reception
0 = No such occurrence
18.3.4.13 Rx Individual Mask Registers (RXIMR0–RXIMR63)
These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not
enabled, one mask register is provided for each available Message Buffer, providing ID masking capability
18-28
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor