PXD10RM Datasheet, PDF (873/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

An interrupt is generated if the BOIE bit in the LINIER is set.
23.8.1.4 Clock gating
The LINFlex clock can be gated from the Mode Entry module (refer to ). In UART mode, the LINFlex
controller acknowledges a clock gating request once the data transmission and data reception are
completed, that is, once the Transmit buffer is empty and the Receive buffer is full.
23.8.2 LIN mode
LIN mode comprises four submodes:
• Master mode
• Slave mode
• Slave mode with identifier filtering
• Slave mode with automatic resynchronization
These submodes are described in the following pages.
23.8.2.1 Master mode
In Master mode the application uses the message buffer to handle the LIN messages. Master mode is
selected when the MME bit in LINCR1 is set.
23.8.2.1.1 LIN header transmission
According to the LIN protocol any communication on the LIN bus is triggered by the Master sending a
header. The header is transmitted by the Master task while the data is transmitted by the Slave task of a
node.
To transmit a header with LINFlex the application must set up the identifier, the data field length and
configure the message (direction and checksum type) in the BIDR before requesting the header
transmission by setting the HTRQ bit in LINCR2.
23.8.2.1.2 Data transmission (transceiver as publisher)
When the master node is publisher of the data corresponding to the identifier sent in the header, then the
slave task of the master has to send the data in the Response part of the LIN frame. Therefore, the
application must provide the data to LINFlex before requesting the header transmission. The application
stores the data in the message buffer BDR. According to the data field length, LINFlex transmits the data
and the checksum. The application uses the CCS bit in the BIDR to configure the checksum type (classic
or enhanced) for each message.
If the response has been sent successfully, the DTF bit in the LINSR is set. In case of error, the DTF flag
is not set and the corresponding error flag is set in the LINESR (refer to Section 23.8.2.1.6, Error
handling).
It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the
data field length in the BIDR is configured with a value higher than 8 data bytes, the DBEF bit in the
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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