PXD10RM Datasheet, PDF (142/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 5-9. Interrupt Status Register (ISR) field descriptions (continued)
Field
28
29
30
31
Description
End of Injected Channel Conversion interrupt (JEOC) flag
It is the interrupt of the digital end of conversion for the injected channel; active when set. When this bit
is set, a JEOC interrupt has occurred.
End of Injected Chain Conversion interrupt (JECH) flag
It is the interrupt of the digital end of chain conversion for the injected channel; active when set. When
this bit is set, a JECH interrupt has occurred.
End of Channel Conversion interrupt (EOC) flag
It is the interrupt of the digital end of conversion. When this bit is set, an EOC interrupt has occurred.
End of Chain Conversion interrupt (ECH) flag
It is the interrupt of the digital end of chain conversion. When this bit is set, an ECH interrupt has
occurred.
5.4.3.2 Channel Pending Registers (CEOCFR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
CEOCFR1 = End of conversion pending interrupt for channel 32 to 63 (extended internal channels)
CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external channels)
Address: Base + 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-8. Channel Pending Register 1 (CEOCFR1)
5-20
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor