PXD10RM Datasheet, PDF (930/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

NOTE
Byte and half-word write accesses are not allowed to this register.
25.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC)
Address 0xC3FD_C02C
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0 PDO 0
0
DFLAON CFLAON
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
SYSCLK
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 25-12. DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please refer to Table 25-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
NOTE
The values of FXOSCON, FMPLL1ON, CFLAON and DFLAON are
retained through STANDBY mode.
25-24
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor