PXD10RM Datasheet, PDF (155/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

5.4.8 Delay registers
5.4.8.1 Decode Signals Delay Register (DSDR)
Reset value: 0x0000_0000
Address: Base + 0x00C4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
DSD[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-24. Decode Signals Delay Register (DSDR)
Table 5-22. Decode Signals Delay Register (DSDR) field descriptions
Field
0:23
24:31
Description
Reserved
Write of any value has no effect, read value is always 0.
DSD[0:7]: Delay between the external decode signals and the start of the sampling phase
It is used to take into account the settling time of the external multiplexer.
The decode signal delay is calculated as: DSD × 1/frequency of system clock
5.4.8.2 Power-down Exit Delay Register (PDEDR)
Reset value: 0x0000_0000
Address: Base + 0x00C8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
W
PDED[0:7]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-25. Power-down Exit Delay Register (PDEDR)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-33