PXD10RM Datasheet, PDF (1019/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 30-10. QSPI_TCR Field Descriptions
Field
Description
SPI_TCNT
SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The
SPI_TCNT field counts the number of SPI transfers the QuadSPI makes. The SPI_TCNT field is
incremented every time the last bit of a SPI frame is transmitted. A value written to SPI_TCNT presets
the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT
field is set in the executing SPI Command. The Transfer Counter wraps around, i.e., incrementing the
counter past 0xFFFF resets the counter to zero.
30.4.3.4 Clock and Transfer Attributes Registers 0 – 1
(QSPI_CTAR0 – QSPI_CTAR1)
The QSPI_CTAR registers are used to define different transfer attribute configurations for the SPI Master
Mode and the SPI Slave Mode. SPI transfers select which one of the QSPI_CTARs to get their transfer
attributes from. In the current implementation there are 2 different QSPI_CTARs selectable. The user must
not write to the QSPI_CTAR registers while the QuadSPI is in the Running state.
In Master Mode, the QSPI_CTAR0 - QSPI_CTAR7 registers define combinations of transfer attributes
such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave
Mode, a subset of the bitfields in the QSPI_CTAR0 and QSPI_CTAR1 registers are used to set the slave
transfer attributes. See the individual bit descriptions for details on which bits are used in Slave Modes.
When the QuadSPI is configured as a SPI Master, the CTAS field in the command portion of the TX FIFO
entry selects which of the QSPI_CTAR register is used. When the QuadSPI is configured as a SPI bus
Slave, the QSPI_CTAR0 register is used.
Address: QSPI_BASE + 0x00C (QSPI_CTAR0)
QSPI_BASE + 0x010 (QSPI_CTAR1)
0
1
R
DBR
W
Reset 0 1
2
3
FMSZ
11
4
5
6
7
8
9
CPO
L
CPHA
LSBFE
PCSSCK
10 0
0
00
10 11
PASC
00
Write: Anytime
12 13 14 15
PDT
PBR
0000
16 17 18 19 20 21
22
23
24 25 26 27 28 29 30 31
R
CSSCK
W
ASC
DT
BR
Reset 0 0 0 0 0 0 0
0
0 0 0 00000
Figure 30-4. Clock and Transfer Attributes Registers 0 – 1 (QSPI_CTAR0 – QSPI_CTAR1)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-15