PXD10RM Datasheet, PDF (532/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

During the appropriate interrupt service routine handling these requests, the interrupt source contained in
the MIR must be explicitly cleared. See Figure 16-5 and Table 16-6.
Register address: ECSM Base + 0x1F
0
1
2
3
4
5
6
7
R
FB0AI
FB0SI
FB1AI
FB1SI
0
0
0
0
W
w1c
w1c
w1c
w1c
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-5. Miscellaneous Interrupt (MIR) Register
Table 16-6. Miscellaneous Interrupt (MIR) Field Descriptions
Name
0
FB0AI
1
FB0SI
2
FB1AI
3
FB1SI
Description
Flash Bank 0 Abort Interrupt
0: A flash bank 0 abort has not occurred.
1: A flash bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing
a 0 has no effect.
Flash Bank 0 Stall Interrupt
0: A flash bank 0 stall has not occurred.
1: A flash bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a
0 has no effect.
Flash Bank 1 Abort Interrupt
0: A flash bank 1 abort has not occurred.
1: A flash bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing
a 0 has no effect.
Flash Bank 1 Stall Interrupt
0: A flash bank 1 stall has not occurred.
1: A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a
0 has no effect.
16.4.2.6 Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as
configuration control for miscellaneous device-level modules. The contents of this register is simply
output from ECSM to other modules where the user-defined control functions are implemented. See
Figure 16-6 and Table 16-7 for the Miscellaneous User-Defined Control Register definition.
16-6
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor