PXD10RM Datasheet, PDF (311/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the application's
operating mode. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first
FIFO access is not supported, and can result in incorrect results.
11.8.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
five entries, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI push TX FIFO register (DSPIx_PUSHR). For more information on
DSPIx_PUSHR. TX FIFO entries can only be removed from the TX FIFO by being shifted out or by
flushing the TX FIFO.
Refer to Section 11.7.2.6, DSPI PUSH TX FIFO Register (DSPIx_PUSHR).
The TX FIFO counter field (TXCTR) in the DSPI status register (DSPIx_SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is
transferred into the shift register from the TX FIFO.
Refer to Section 11.7.2.4, DSPI Status Register (DSPIx_SR) for more information on DSPIx_SR.
The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPIx_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the DSPIx_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
11.8.3.4.1 Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPIx_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPIx_SR is set. The
TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates that a write to
DSPIx_PUSHR is complete or alternatively by host software writing a 1 to the TFFF in the DSPIx_SR.
The TFFF can generate a DMA request or an interrupt request.
Refer to Section 11.8.7.2, Transmit FIFO Fill Interrupt or DMA Request (TFFF), for details.
The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is unchanged.
No error condition is indicated.
11.8.3.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPIx_SR is set to indicate the
completion of a transfer. The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPIx_MCR.
If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is
empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPIx_SR is set.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-29