PXD10RM Datasheet, PDF (1220/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Int
Vectors
External IRQ_1¹
External IRQ_0
OR
OR
Interrupt enable
Glitch filter Prescaler
IFCP[3:0]
Glitch filter Counter_n
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[13:0]¹
EIF[13:8]¹
EIF[7:0]
Edge Detection
Glitch Filter
Pads
Figure 37-21. External interrupt pad diagram
1 _{This value is valid in the 176-pin LQFP and the 208-pin packages}
IRE[13:0]¹
Interrupt Edge Enable
Rising
IREE[13:0]¹
Falling
IFEE[13:0]¹
37.6.4.1 External interrupt management
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt
Request Enable Register (IRER - Section 37.5.3.4, Interrupt Request Enable Register (IRER)). A pad
defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an
active falling edge or both edges being active. A setting of having both edge events disabled is reserved
and should not be configured. External interrupts require that the associated input buffer for the pad is
enabled (PCR[IBE]=1).
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag which is held in the Flag register (ISR -
Section 37.5.3.3, Interrupt Status Flag Register (ISR))”. This register is a clear-by-write-1 register type,
preventing inadvertent overwriting of other flags in the same register. The external interrupt flags map to
the INTC vector table as follows:
• EIF[7:0] map to the External IRQ_0 vector
• EIF[13:8] map to the External IRQ_1 vector
37.7 Pin muxing
For pin muxing, please see Chapter 3, Signal Description,” of this document.
37-26
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor