PXD10RM Datasheet, PDF (947/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

25.4.3.3 Peripheral Clocks Disable
On completion of the Target Mode Request, the MC_ME requests each peripheral to enter its stop mode
when:
• the peripheral is configured to be disabled via the target mode, the peripheral configuration
registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers
ME_PCTL0…143
WARNING
The MC_ME does not automatically request peripherals to enter their stop
modes if the power domains in which they are residing are to be turned off
due to a mode change. Therefore, it is software’s responsibility to ensure
that those peripherals that are to be powered down are configured in the
MC_ME to be frozen.
Each peripheral acknowledges its stop mode request after closing its internal activity. The MC_ME then
disables the corresponding clock(s) to this peripheral.
In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals to
acknowledge the stop requests. The SAFE mode clock gating configuration is applied immediately
regardless of the status of the peripherals’ stop acknowledges.
Please refer to Section 25.4.6, Peripheral clock gating for more details.
Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these
outputs are forced to a safe or recessive state when the device enters the SAFE mode.
25.4.3.4 Processor Low-Power Mode Entry
If, on completion of the Peripheral Clocks Disable, the mode transition is to the HALT mode, the MC_ME
requests the processor to enter its halted state. The processor acknowledges its halt state request after
completing all outstanding bus transactions.
If, on completion of the Peripheral Clocks Disable, the mode transition is to the STOP or STANDBY
mode, the MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop
state request after completing all outstanding bus transactions.
25.4.3.5 Processor and System Memory Clock Disable
If, on completion of the Processor Low-Power Mode Entry, the mode transition is to the HALT, STOP, or
STANDBY mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the
processor and system memory clocks to achieve further power saving.
The clocks to the processor and system memories are unaffected for all transitions between software
running modes including DRUN, RUN0…3, and SAFE.
WARNING
Clocks to the whole device including the processor and system memories
can be disabled in TEST mode.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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