PXD10RM Datasheet, PDF (655/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

As noted in Section 17.4.4.7, Flash Error Response Operation”, a page buffer is not marked as valid if the
flash array access terminated with any type of transfer error. However, the result is that flash array accesses
that are tagged with a single-bit correctable ECC event are loaded into the page buffer and validated. For
additional comments on this topic, see Section 17.4.4.8.4, Buffer Invalidation”.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the PFLASH2P_LCA may trigger a prefetch to the next
sequential page of array data on the first idle cycle following the request. The access address is
incremented to the next-higher 16-byte boundary, and a flash array prefetch is initiated if the data is not
already resident in a page buffer. Prefetched data is always loaded into the least-recently-used buffer.
Buffers may be in one of six states, listed here in prioritized order:
9. Invalid - the buffer contains no valid data
10. Used - the buffer contains valid data which has been provided to satisfy an AHB burst type read
11. Valid - the buffer contains valid data which has been provided to satisfy an AHB single type read
12. Prefetched - the buffer contains valid data which has been prefetched to satisfy a potential future
AHB access
13. Busy AHB - the buffer is currently being used to satisfy an AHB burst read
14. Busy Fill - the buffer has been allocated to receive data from the flash array, and the array access
is still in progress
Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:
1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple
invalid buffers, the one to be used is selected using a simple numeric priority, where buffer 0 is
selected first, then buffer 1, etc.
2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.
Once the candidate page buffer has been selected, the flash array is accessed and read data loaded into the
buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as
most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line
address after a buffer hit, the recently-used status is not changed. Rather, it is marked as
most-recently-used only after a subsequent buffer hit.
This policy maximizes performance based on reference patterns of flash accesses and allows for
prefetched data to remain valid when non-prefetch enabled bus masters are granted flash access.
Multiple algorithms are available for prefetch control which trade off performance versus power. They are
defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive prefetching increases power
slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering
average read latency.
In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer
enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either
instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Recall the prefetch
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-105