PXD10RM Datasheet, PDF (905/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

24.4 Initialization Information
The reset state of MPU_CESR[VLD] disables the entire module. Recall while the MPU is disabled, all
accesses from all bus masters are allowed. This state also minimizes the power dissipation of the MPU.
The power dissipation of each access evaluation macro is minimized when the associated region descriptor
is marked as invalid or when MPU_CESR[VLD] = 0.
Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup,
including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. Recall if a
memory reference does not hit in any region descriptor, the attempted access is terminated with an error.
24.5 Application Information
In an operational system, interfacing with the MPU can generally be classified into the following activities:
1. Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGDn, it would typically be
performed using four 32-bit word writes. As discussed in Section 24.2.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3)”, the hardware assists in the maintenance of the valid
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed simply by clearing
MPU_RGDn.Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAACn) would typically be performed.
Recall writes to the region descriptor using this alternate access control location do not affect the
valid bit, so there are, by definition, no coherency issues involved with the update. The access
rights associated with the memory region switch instantaneously to the new value as the IPS write
completes.
3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
5. When the MPU detects an access error, the current AHB bus cycle is terminated with an error
response and information on the faulting reference captured in the MPU_EARn and MPU_EDRn
registers. The error-terminated AHB bus cycle typically initiates some type of error response in the
originating bus master. For example, a processor core may respond with a bus error exception,
while a data movement bus master may respond with an error interrupt. In any event, the processor
can retrieve the captured error address and detail information simply be reading the
MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is
signaled by MPU_CESR[SPERR].
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
24-19