PXD10RM Datasheet, PDF (77/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

(see detail inset) PA10 1
(see detail inset) PA11 2
(see detail inset) PA12 3
(see detail inset) PA13 4
(see detail inset) PA14 5
(see detail inset) PA15 6
VDDE_A 7
VSSE_A 8
(see detail inset) PG0 9
(see detail inset) PG1 10
(see detail inset) PG2 11
(see detail inset) PG3 12
(see detail inset) PG4 13
(see detail inset) PG5 14
FP1/DCU_B6/GPIO[92]/PG6 15
FP0/DCU_B7/GPIO[93]/PG7 16
(see detail inset) PG8 17
(see detail inset) PG9 18
BP2/DCU_DE/GPIO[96]/PG10 19
(see detail inset) PG11 20
VLCD/GPIO[104]/PH5 21
VDDR 22
176-Pin
VSSR 23
RESET 24
LQFP
VRC_CTRL 25
VPP
XTAL
26
27
Detail:
VSSOSC 28
FP13/eMIOSB20/DCU_G2/GPIO[10]/PA10 –
EXTAL 29
FP12/eMIOSA13/DCU_G3/GPIO[11]/PA11 –
VSSPLL 30
FP11/eMIOSA12/DCU_G4/GPIO[12]/PA12 –
VDDPLL 31
FP10/eMIOSA11/DCU_G5/GPIO[13]/PA13 –
VREG_BYPASS 32
FP9/eMIOSA10/DCU_G6/GPIO[14]/PA14 –
PDI10/MCKO/GPIO[123]/PK2 33
FP8/eMIOSA9/DCU_G7/GPIO[15]/PA15 –
PDI11/MSEO/GPIO[124]/PK3 34
FP7/SOUND/SCL_3/DCU_B0/GPIO[86]/PG0 –
PDI12/EVTO/GPIO[125]/PK4 35
FP6/SDA_3/DCU_B1/GPIO[87]/PG1 –
TDI/GPIO[100]/PH1 36
FP5/eMIOSB19/DCU_B2/GPIO[88]/PG2 –
PDI13/EVTI/GPIO[126]/PK5 37
FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 –
PDI14/MDO0/GPIO[127]/PK6 38
FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 –
TDO/GPIO[101]/PH2 39
FP2/eMIOSA8/DCU_B5/GPIO[91]/PG5 –
PDI15/MDO1/GPIO[128]/PK7 40
BP0/DCU_VSYNC/GPIO[94]/PG8 –
TMS/GPIO[102]/PH3 41
BP1/DCU_HSYNC/GPIO[95]/PG9 –
PDI16/MDO2/GPIO[129]/PK8 42
BP3/DCU_PCLK/GPIO[97]/PG11 –
TCK/GPIO[99]/PH0 43
PDI17/MDO3/GPIO[130]/PK9 44
132 PB11/GPIO[27]/CANTX_1/PDI3/eMIOSA16
131 PB10/GPIO[26]/CANRX_1/PDI2/eMIOSA23
130 PB0/GPIO[16]/CANTX_0/PDI1
129 PB1/GPIO[17]/CANRX_0/PDI0
128 PJ11/GPIO[116]/PDI7
127 PJ10/GPIO[115]/PDI6
126 PJ9/GPIO[114]/PDI5
125 PJ8/GPIO[113]/PDI4
124 VSS12
123 VDD12
122 PJ3/GPIO[108]/PDI_PCLK
121 PJ2/GPIO[107]/PDI_VSYNC
120 PJ1/GPIO[106]/PDI_HSYNC
119 PJ0/GPIO[105]/PDI_DE
118 PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8
117 PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9
116 PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10
115 PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11
114 VSSMC
113 VDDMC
112 PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12
111 PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13
110 PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14
109 PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15
108 PD15/GPIO[61]/M3C1P/SSD3_3
107 PD14/GPIO[60]/M3C1M/SSD3_2
106 PD13/GPIO[59]/M3C0P/SSD3_1
105 PD12/GPIO[58]/M3C0M/SSD3_0
104 VSSMB
103 VDDMB
102 PD11/GPIO[57]/M2C1P/SSD2_3
101 PD10/GPIO[56]/M2C1M/SSD2_2
100 PD9/GPIO[55]/M2C0P/SSD2_1
99 PD8/GPIO[54]/M2C0M/SSD2_0
98 PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16
97 PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17
96 PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18
95 PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19
94 VSSMA
93 VDDMA
92 PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20
91 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21
90 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22
89 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
Figure 3-2. LQFP 176-pin configuration (top view)¹
1. Availability of port pin alternate functions depends on product selection
PXD10 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
3-3
Preliminary—Subject to Change Without Notice