PXD10RM Datasheet, PDF (982/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Independent timeout periods for each timer
27.2 Signal description
The PIT module has no external pins.
27.3 Memory map and register description
This section provides a detailed description of all registers accessible in the PIT module.
27.3.1 Memory map
Table 27-1 gives an overview on all PIT registers.
Table 27-1. PIT memory map
Address Offset
0x000
0x004 - 0x0FC
0x100 - 0x10C
0x110 - 0x11C
0x120 - 0x12C
0x130 - 0x13C
0x140 - 0x1FC
1 _{See Table 27-2}
Use
PIT Module Control Register
Reserved
Timer Channel 0
Timer Channel 1
Timer Channel 2
Timer Channel 3
Reserved
Access
R/W
R
1
1
1
1
R
Address Offset
channel + 0x00
channel + 0x04
channel + 0x08
channel + 0x0C
Table 27-2. Timer Channel n
Use
Timer Load Value Register
Current Timer Value Register
Timer Control Register
Timer Flag Register
Access
R/W
R
R/W
R/W
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
NOTE
Reserved registers will read as 0, writes will have no effect.
27-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor