PXD10RM Datasheet, PDF (572/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-15. SLL field descriptions (continued)
Field
Description
16:31
SLK15-0: Secondary Low address space block locK 15-0 (Read/Write)
These bits are used as an alternate means to lock the blocks of Low Address Space from Program and
Erase.
For Code Flash 0, SLK5-0 are related to sectors B0F5-0, respectively.
For Code Flash 1, SLK1-0 are related to sectors B2F1-0, respectively.
A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for Program and
Erase.
A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive Program
and Erase pulses.
The SLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the SLK register is not writable if a high voltage operation
is suspended.
Upon reset, information from the Test Flash block is loaded into the SLK registers. The SLK bits may be
written as a register. Reset will cause the bits to go back to their Test Flash block value. The default value
of the SLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SLK bits will default
to locked, and will not be writable. The reset value will always be 1 (independent of the Test Flash block),
and register writes will have no effect.
In Code Flash 0 bits SLK15-6 are read-only and locked at 1.
In Code Flash 1, bits SLK15-2 are read-only and locked at 1.
SLK is not writable unless SLE is high.
0: Low Address Space Block is unlocked and can be modified (if also LML.LLK=0).
1: Low Address Space Block is locked and cannot be modified.
17.2.6.8 Low/Mid address space block Select register (LMS)
Address Offset: 0x00010
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0 MSL1 MSL0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0
r/0 rw/0 rw/0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LSL15 LSL14 LSL13 LSL12 LSL11 LSL10 LSL9 LSL8 LSL7 LSL6 LSL5 LSL4 LSL3 LSL2 LSL1 LSL0
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-7. Low/Mid address space block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on
during erase.
Table 17-16. LMS field descriptions
Field
Description
0:13 Reserved (Read Only).
Write these bits has no effect and read these bits always outputs 0.
17-22
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor