PXD10RM Datasheet, PDF (284/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.3 Overview
The register content is transmitted using an SPI protocol. There are two identical DSPI modules (DSPI 0
and DSPI 1) on the device.
For queued operations the SPI queues reside in internal SRAM which is external to the DSPI. Data
transfers between the queues and the DSPI FIFOs are accomplished through the use of the eDMA
controller or through host software.
Figure 11-2 shows a DSPI with external queues in internal SRAM.
Internal SRAM
RX queue
TX queue
Address/control
RX data
TX data
eDMA controller
or host CPU
Address/control
TX data
RX data
DSPI
TX FIFO RX FIFO
Shift register
Figure 11-2. DSPI with Queues and eDMA
11.4 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode
• Buffered transmit and receive operation using the TX and RX FIFOs, with depths of five entries
• Visibility into TX and RX FIFOs for ease of debugging
• FIFO bypass mode for low-latency updates to SPI queues
11-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor