PXD10RM Datasheet, PDF (324/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
CS
t_DT
t_DT = 1 SCK.
Figure 11-21. Continuous SCK Timing Diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal
for the next transfer is the same as for the current transfer. Under certain conditions, SCK can continue
with PCS asserted, but with no data being shifted out of SOUT (SOUT pulled high). This can cause the
slave to receive incorrect data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering STOPPED state (refer to Section 11.8.2, Start and
Stop of DSPI Transfers”).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode.
Figure 11-22 shows timing diagram for continuous SCK format with continuous selection enabled.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1
Transfer 2
Figure 11-22. Continuous SCK Timing Diagram (CONT=1)
11-42
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor