PXD10RM Datasheet, PDF (412/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Figure 12-60. Example of layer placement with 3-layer blending
All blending is performed using full 8-bits-per-component colors. The DCU automatically performs a
color promotion on source data that is stored in less than RGB888 color.
12.4.5.2 Control Descriptors
The control descriptor for each layer consists of seven registers, and all 16 control descriptors are identical
except the two highest priority layers, which have additional control bits for the safety mode.
The control descriptors may be written to at any time, and the value present in the registers at the start of
the next frame refresh cycle defines the content of the panel for that frame. To avoid coherency issues,
ensure all control descriptor changes are made before the PROG_END bit in the INT_STATUS register is
asserted.
12.4.5.3 Layer size and positioning
The size of each layer is defined by register 1 in the control descriptor for the layer (CTRLDESCLn_1,
where n is the layer number). The register contains two bit fields, HEIGHT and WIDTH, which determine
the size and shape of the layer. Both fields are expressed in terms of the number of pixels in each
dimension.
The HEIGHT bit field may take any value; however, it may not be useful to define a value larger than the
height of the panel.
The WIDTH field has a restriction on the value it can take, depending on the data format of the graphic
specified by the layer. This field must always be an integer multiple of the number of pixels that are
represented by a 32-bit word except in the special case of 1 bit per pixel where the multiple is 16.. The data
format can range from 1 bit per pixel to 32 bits per pixel and so there is a range of multiples from 1 to 32.
Figure 12-53 shows the multiples for the WIDTH bit field and some correct values.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor