PXD10RM Datasheet, PDF (781/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

interrupt_exception_handler_continuedx:
code to create stack frame, save working register, and save SRR0 and SRR1
wrteei 1
# enable processor recognition of interrupts
code to save rest of context required by e500 EABI
bl
ISRx
# branch to ISR for interrupt with vector x
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar
# ensure store to clear flag bit has completed
lis
r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address
li
r4,0x0
# form 0 to write to INTC_EOIR
wrteei 0
# disable processor recognition of interrupts
stw
r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr
# branch to epilog
21.7.3 ISR, RTOS, and task hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register
(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme
that it may have, but that priority scheme is independent and has a lower priority of execution than the
priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside
the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at
different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.
An ISR whose PRIn in INTC priority select registers (INTC_PSR0_3–INTC_PSR204_206) has a value
of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt
request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit
will cause it to remain negated, which consequently also will not cause an interrupt request to the
processor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another
ISR or the interrupt exception handler, perhaps after executing another ISR.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-29