PXD10RM Datasheet, PDF (330/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Refer to Section 11.8.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism, and
Section 11.8.3.5, Receive First In First Out (RX FIFO) Buffering Mechanism, for details on the FIFO
operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
Figure 11-23 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter.
Push TX FIFO
register
TX FIFO base
–
–
Entry A (first in)
Entry B
Entry C
Entry D (last in)
–
–
Transmit next
data pointer
(TXNXTPTR)
Shift register
SOUT
+1
TX FIFO counter
–1
Figure 11-23. TX FIFO Pointers and Counter
11.9.4.1 Address Calculation for the First-in Entry and Last-in Entry in the TX
FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
First-in entry address = TXFIFO base + 4 (TXNXTPTR)
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Last-in entry address = TXFIFO base + 4 x [(TXCTR + TXNXTPTR - 1) modulo TXFIFO depth]
where:
TXFIFO base = base address of transmit FIFO
TXCTR = transmit FIFO counter
TXNXTPTR = transmit next pointer
TX FIFO depth = transmit FIFO depth, implementation specific
11.9.4.2 Address Calculation for the First-in Entry and Last-in Entry in the RX
FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
First-in entry address = RXFIFO base + 4 x (POPNXTPTR)
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Last-in entry address = RXFIFO base + 4 x [(RXCTR + POPNXTPTR - 1) modulo RXFIFO depth]
where:
RXFIFO base = base address of receive FIFO
11-48
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor