PXD10RM Datasheet, PDF (290/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 11-3. DSPIx_MCR Field Descriptions (continued)
Field
4
FRZ
Description
Freeze. Enables the DSPI transfers to be stopped on the next frame boundary when the device
enters debug mode.
5
MTFE
0 Do not halt serial transfers
1 Halt serial transfers
Modified timing format enable. Enables a modified transfer format to be used. Refer to
Section 11.8.5.4, Modified SPI Transfer Format (MTFE = 1, CPHA = 1), for more information.
6
7
ROOE
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
Reserved. This bit is writable, but has no effect.
Receive FIFO overflow overwrite enable. Enables an RX FIFO overflow condition to ignore the
incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is received, the
data from the transfer that generated the overflow is ignored or put in the shift register.
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the
incoming data is ignored. Refer to Section 11.8.7.6, Receive FIFO Overflow Interrupt Request
(RFOF), for more information.
8–9
10–15
PCSISn
0 Incoming data is ignored
1 Incoming data is put in the shift register
Reserved, but implemented. These bits are writable, but have no effect.
Peripheral chip select inactive state. Determines the inactive state of the CS0_x signal. CS0_x must
be configured as inactive high for slave mode operation.
16
17
MDIS
0 The inactive state of CS0_x is low
1 The inactive state of CS0_x is high
Reserved.
Module disable. Allows the clock to stop to the non-memory mapped logic in the DSPI, effectively
putting the DSPI in a software controlled power-saving state. Refer to Section 11.8.8, Power Saving
Features,” for more information. The reset value of the MDIS bit is parameterized, with a default
reset value of 0.
18
DIS_TXF
0 Enable DSPI clocks
1 Allow external logic to disable DSPI clocks
Disable transmit FIFO. Enables and disables the TX FIFO. When the TX FIFO is disabled, the
transmit part of the DSPI operates as a simplified double-buffered SPI. Refer to Section 11.8.3.3,
FIFO Disable Operation,” for details.
19
DIS_RXF
0 TX FIFO is enabled
1 TX FIFO is disabled
Disable receive FIFO. Enables and disables the RX FIFO. When the RX FIFO is disabled, the
receive part of the DSPI operates as a simplified double-buffered SPI. Refer to Section 11.8.3.3,
FIFO Disable Operation,” for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
11-8
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor